In the 8085 microprocessor, the higher order address lines are directly available, but the lower order address lines are multiplexed with data bus in time sharing. Hence, the de-multiplexing of address/data bus is required for separation of address and data bus.

In earlier clock cycle state of every machine cycle, the content on AD0 – AD7 is the lower order address from A0 to A7 and the LE also goes high. Later clock cycle state, the 8085 remove the content of AD0-AD7 lines and use same lines as a data lines for next clock cycle state onward.

Hence, the de-multiplexing of address/data bus can be implemented by using tri-state octal latch 74LS373 and this latch can be controlled by using ALE signal of 8085. When ALE goes high, the address signal will be latched in the octal latch 74LS373 and output of the latch will be provided on A0-A7.


When ALE goes low, the latch will be disabled and the AD0-AD7 can be used as data bus D0-D7.